![]() ![]() This all affects what Power10 is and what Power11 will be.īack in 2012, we weren’t talking about storage class memory, but it obviously came up on the scene. We don’t have the infinite wherewithal to do everything all at once, so we actually have to plan and stage our innovations over time. William Starke: The next processor in the line always comes from many starting points, and it is always a byproduct of what were we thinking about when we did Power10 and perhaps either it wasn’t the right time for a particular technology or the trends hadn’t converged with the economics at that point. TPM: In your view, what is the right time to do these things? IBM has used chiplets to create certain Power8 and Power9 sockets, Power10 is largely done, so what is Power11? We are dipping our toe into any number of technological options on how to move forward and you are seeing other folks in the industry dip their toes into the waters. ![]() We are not going to get around Moore’s Law, we can’t increase the size of chips because of the cost and the drop in yields, but with chiplets we are going to be able to use process in the best possible ways and create a complex of processing and networking and I/O that gives you the best performance profile and cost. Is this going to be the normal thing? That’s a good question. ![]() William Starke: Architecturally, it’s interesting we have been thinking about chiplet architectures. So, given all of this, what do you do for Power10 and beyond? With Samsung, IBM has a foundry partner who is going to be around and is committed to its process roadmap to advance memory and flash and they’re going to deliver on 7 nanometer and onwards. IBM does not need to win the big supercomputer deals to fund future Power chip development or to even have a sizable presence in HPC as we know it. So I think we’ve got that down, with the business humming along at more than $2.5 billion a year and growing again. I don’t think there’s a question that IBM is committed to the Power chip roadmap anymore. ![]() I am also hearing that IBM will be embedding more acceleration, particularly for machine learning algorithms, with Power10. So your way of buffering memory and abstracting the memory interface, as you did in Power8 and Power9 processors, and putting it into the buffer chip could become the the normal way of creating main memory, and this updated Power9 chip is a preview of the memory that will go mainstream across the Power Systems line with Power10. I was intrigued by the idea that the memory buffer chip you have created will become a kind of a standard in the industry, maybe with DDR5. I believe this is code-named “Axone,” which is a play on the acronym you use to describe the SERDES based I/O and memory controllers you will be extending with the Power9 kicker coming later this year. Timothy Prickett Morgan: As you know, we have gone into the architecture of the Power9 processor in great detail, and I have been intrigued by some of the ideas that you are going to be putting into the third iteration of the Power9 chip, the follow-on to the “Nimbus” chip[ for scale out machines and the “Cumulus” chip for scale up machines. The Next Platform went down to Austin recently to visit the Power Systems team, and had a chat with Starke about how IBM is thinking about its future Power processors. Now, Starke has steered the development of the Power10 chip after being heavily involved in Power9 and is well on the way to mapping out what Power11 might look like and way off in the distance has some ideas about what Power12 might hold. Starke started out at IBM in 1990 as a mainframe performance analysis engineer in the Poughkeepsie, New York lab and made the jump to the Austin Lab where the development for the AIX variant of Unix and the Power processors that run it is centered, first focusing on the architecture and technology of future systems and then Power chip performance and then shifting to being one of the Power chip architects a decade ago. But all of these challenges are what get hardware and software engineers out of bed in the morning. It seems to be getting more difficult over time, not less so, as the diversifying needs of customers run up against the physical reality of the Moore’s Law process shrink wall and the economics of designing and manufacturing server processors in the second and soon to be the third decade of the 21st century. Starke knows the enterprise grade variants of the Power architecture designed by IBM about as well as anyone on Earth does, and is acutely aware of the broad and deep set of customer needs that IBM always has to address with each successive Power chip generation. As the lead engineer on the Power10 processor, Bill Starke already knows what most of us have to guess about Big Blue’s next iteration in a processor family that has been in the enterprise market in one form or another for nearly three decades. ![]()
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